industrial temperature range idt74lvch16276a 3.3v cmos 12-bit synchronous bus exchanger 1 january 2004 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-4230/6 features: ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ? cmos power levels (0.4 w typ. static) ? all inputs, outputs, and i/o are 5v tolerant ? supports hot insertion ? available in tssop package functional block diagram applications: ? 5v and 3.3v mixed voltage systems ? data communication and telecommunication systems drive features: ? high output drivers: 24ma ? reduced system switching noise idt74lvch16276a 3.3v cmos 12-bit synchronous bus exchanger with bus-hold and 5 volt tolerant i/o ce1b clk cea1b sel oeb cea2b a 1:12 ce2b a-1b register 1b-a register m u x 1 0 12 12 12 12 12 12 1b 1:12 2b 1:12 12 oea ce d ce q q d control register 2b-a register ce q d a-2b register ce d q 12 12 1 29 56 28 30 27 55 2 description: the lvch16276a synchronous bus exchanger is built using advanced dual metal cmos technology.the lvch16276a is a high-speed, bidirectional, 12-bit, registered, bus multiplexer for use in synchronous memory interleaving applications. all registers have a common clock and use a clock enable ( cexxx ) on each data register to control data sequenc- ing. the output enables and mux select ( oea , oeb and sel) are also under synchronous control allowing direction changes to be edge trig- gered events. the tri-port bus exchanger has three 12-bit ports. data may be transferred between the a port and either/both of the b ports. the clock enable ( ce1b , ce2b , cea1b and cea2b ) inputs control the data storage. both b ports have a common output enable ( oeb ) to aid in synchronously loading the b registers from the b port. all pins of the lvch16276a can be driven from either 3.3v or 5v devices. this feature allows the use of this device as a translator in a mixed 3.3v/5v supply system. the lvch16276a has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. the lvch16276a has ?bus-hold? which retains the inputs? last state whenever the input goes to a high impedance. this prevents floating inputs and eliminates the need for pull-up/down resistors.
industrial temperature range 2 idt74lvch16276a 3.3v cmos 12-bit synchronous bus exchanger tssop top view pin configuration symbol description max unit v term terminal voltage with respect to gnd ?0.5 to +6.5 v t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, ?50 ma i ok v i < 0 or v o < 0 i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. as applicable to the device type. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 6.5 8 pf c i/o i/o port capacitance v in = 0v 6.5 8 pf capacitance (t a = +25c, f = 1.0mhz) cea1b 2b 3 gnd 2b 2 2b 1 v cc a 1 a 2 gnd a 3 a 4 a 5 a 6 a 8 a 9 gnd a 10 a 11 a 12 v cc 1b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 49 50 51 52 53 54 55 56 1 ce1b 2b 4 gnd 2b 5 2b 6 v cc 2b 7 2b 8 2b 9 2b 10 2b 11 2b 12 gnd 1b 11 1b 10 1b 9 1b 8 gnd 1b 7 1b 6 1b 5 gnd 1b 3 oea sel 25 26 27 28 32 31 30 29 gnd 1b 4 oeb clk a 7 1b 2 v cc 1b 12 cea2b ce2b
industrial temperature range idt74lvch16276a 3.3v cmos 12-bit synchronous bus exchanger 3 inputs outputs ax cea1b cea2b oeb clk 1bx 2bx hlll hh llll ll hlhl hb (2) llhl lb (2) hh ll b (2) h lh ll b (2) l xhhl b (2) b (2) xxxh zz xxxl active active function tables (1) inputs outputs 1bx 2bx sel ce1b ce2b oea clk ax hxhlx l h lxhlx l l xxhhx l a (2) xhlxl l h xllxl l l xxlxh l a (2) x xxxx h z notes: 1. h = high voltage level l = low voltage level x = don?t care z = high-impedance = low-to-high transition 2. a, b = output level before the indicated steady-state input conditions were established. pin description signal i/o description a (1:12) i/o bidirectional data port a. usually connected to the cpu?s address/data bus. (1) 1b (1:12) i/o bidirectional data port 1b. usually connected to the even path or even bank of memory. (1) 2b (1:12) i/o bidirectional data port 2b. usually connected to the odd path or odd bank of memory. (1) clk i clock input. cea1b i clock enable input for the a-1b register. if cea1b is low during the rising edge of clk, data will be clocked into register a-1b (active low). cea2b i clock enable input for the a-2b register. if cea2b is low during the rising edge of clk, data will be clocked into register a-2b (active low). ce1b i clock enable input for the 1b-a register. if ce1b is low during the rising edge of clk, data will be clocked into register 1b-a (active low). ce2b i clock enable input for the 2b-a register. if ce2b is low during the rising edge of clk, data will be clocked into register 2b-a (active low). sel i 1b or 2b part selection. when high during the rising edge of clk, sel enables data transfer from 1b port to a port. when l ow during the rising edge of clk, sel enables data transfer from 2b port to a port. oea i synchronous output enable for a port (active low). oeb i synchronous output enable for 1b port and 2b port (active low). note: 1. these pins have ?bus-hold?. all other pins are standard inputs, outputs, or i/os.
industrial temperature range 4 idt74lvch16276a 3.3v cmos 12-bit synchronous bus exchanger symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input leakage current v cc = 3.6v v i = 0 to 5.5v ? ? 5a i il i ozh high impedance output current v cc = 3.6v v o = 0 to 5.5v ? ? 10 a i ozl (3-state output pins) i off input/output power off leakage v cc = 0v, v in or v o 5.5v ? ? 50 a v ik clamp diode voltage v cc = 2.3v, i in = ?18ma ? ?0.7 ?1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl quiescent power supply current v cc = 3.6v v in = gnd or v cc ?? 10a i cch i ccz 3.6 v in 5.5v (2) ?? 10 i cc quiescent power supply current one input at v cc - 0.6v, other inputs at v cc or gnd ? ? 500 a variation dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c notes: 1. typical values are at v cc = 3.3v, +25c ambient. 2. this applies in the disabled state only. bus-hold characteristics symbol parameter (1) test conditions min. typ. (2) max. unit i bhh bus-hold input sustain current v cc = 3v v i = 2v ? 75 ? ? a i bhl v i = 0.8v 75 ? ? i bhh bus-hold input sustain current v cc = 2.3v v i = 1.7v ? ? ? a i bhl v i = 0.7v ? ? ? i bhho bus-hold input overdrive current v cc = 3.6v v i = 0 to 3.6v ? ? 500 a i bhlo notes: 1. pins with bus-hold are identified in the pin description. 2. typical values are at v cc = 3.3v, +25c ambient.
industrial temperature range idt74lvch16276a 3.3v cmos 12-bit synchronous bus exchanger 5 note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 6ma 2 ? v cc = 2.3v i oh = ? 12ma 1.7 ? v cc = 2.7v 2.2 ? v cc = 3v 2.4 ? v cc = 3v i oh = ? 24ma 2.2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 6ma ? 0.4 i ol = 12ma ? 0.7 v cc = 2.7v i ol = 12ma ? 0.4 v cc = 3v i ol = 24ma ? 0.55 operating characteristics, v cc = 3.3v 0.3v, t a = 25c symbol parameter test conditions typical unit c pd power dissipation capacitance per bus exchanger outputs enabled c l = 0pf, f = 10mhz pf c pd power dissipation capacitance per bus exchanger outputs disabled
industrial temperature range 6 idt74lvch16276a 3.3v cmos 12-bit synchronous bus exchanger notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction. switching characteristics (1) v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. unit t plh propagation delay 1.5 6.6 1.5 5.7 ns t phl clk to 1bx or clk to 2bx t plh propagation delay sel stable, cexb enabled 1.5 7 1.5 5.8 ns t phl clk to ax sel changing, cexb disabled 1.5 7.5 1.5 6.5 sel changing, cexb enabled 1.5 7.6 1.5 6.6 t pzh output enable time 1.5 6.8 1.5 5.8 ns t pzl clk to ax, clk to 1bx, or clk to 2bx t phz output disable time 1.5 6.6 1.5 6.6 ns t plz clk to ax, clk to 1bx, or clk to 2bx t su set-up time, high or low data to clk 1.5 ? 1.5 ? ns t su set-up time, oea to clk, oeb to clk 1.5 ? 1.5 ? ns t su set-up time, sel to clk 1.5 ? 1.5 ? ns t su set-up time, cea1b to clk, ce1b to clk , 1.8 ? 1.8 ? ns ce2b to clk, or cea2b to clk t h hold time, clk to data 1 ? 1 ? ns t h hold time, clk to oea , clk to oeb , clk to sel 1 ? 1 ? ns t h hold time, clk to cea1b , clk to ce1b , 0.7 ? 0.7 ? ns clk to ce2b , clk to cea2b t w pulse width, clk high 2.5 ? 2.5 ? ns t sk (o) output skew (2) ? 500 ? 500 ps
industrial temperature range idt74lvch16276a 3.3v cmos 12-bit synchronous bus exchanger 7 open v load gnd v cc pulse generator d.u.t. 500 500 c l r t v in v out (1, 2) lvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 lvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t lvc link data input 0v 0v 0v 0v t rem timing input asynchronous control synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t lvc link low-high-low pulse high-low-high pulse v t t w v t lvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz lvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 10mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 10mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range 8 idt74lvch16276a 3.3v cmos 12-bit synchronous bus exchanger ordering information idt xx lvc xxxx xx package device type temp. range pa 16 74 thin shrink small outline package 12-bit synchronous bus exchanger -40c to +85c xxx family bus-hold 276a bus-hold double-density, 24ma h corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com
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